Available Thesis Topics
When applying for a thesis topic, follow the procedure described here and CC the advisor(s) in your email.
Click on a topic for more details.
Note: Some topics are marked as “B.Sc.” level, but we might make an extended version for M.Sc. students if you are really interested.
Note: This topic is not available for Winter Semester 2025
In a NUMA system, kernel text is distributed across all nodes. This causes latency overhead when userspace applications require access to kernel functions, because the memory might be located on another node. A solution has been proposed on the Linux Kernel Mailing List to tackle this problem, which is to replicate kernel text across all NUMA nodes.
Goal of this thesis: In this thesis, you’ll work directly inside the Linux Kernel. You will apply and test a provided kernel patchset. You’ll use virtualisation tools and a real NUMA server to execute and benchmark the new kernel. Based on your observations, you will propose improvements to the solution.
- Evaluate the patch with a set of defined benchmarks (or develop new benchmarks)
- Find ways to extend and improve the patch
Target: M.Sc. students
Prerequisites:
- Programming language: C
- Linux Kernel Programming
Advisor: Jérôme Coquisart
Note: This topic is not available for Winter Semester 2025
Most operating systems provide a page cache to store data accessed from storage devices in memory, enabling faster future access. This cache is a critical component for the performance of I/O-intensive applications.
On modern NUMA (Non-Uniform Memory Access) systems, not all memory is equal, accesses to the local NUMA node are faster than accesses to remote nodes. Consequently, the location of the page cache can significantly affect performance.
Goals of this thesis: Within the context of an ongoing group project developing a NUMA-aware page cache, you will design and implement an evaluation framework to assess its performance. This involves creating profiling tools to measure memory usage, access locality, and performance, as well as developing micro-benchmarks to test specific components and features of the memory subsystem.
Your profiler should be able to answer, for any given application:
- Where is the page cache located relative to the application?
- What is the application’s access pattern?
- How I/O-intensive is the application?
- Is the operating system performing page migration in the background?
Target: B.Sc. students
Prerequisites:
- Programming language: C
- Background: Linux Kernel Programming
Advisor: Jérôme Coquisart
In the last few years, ARM-based CPUs have greatly improved in terms of performance, challenging the x86 domination, while also having better efficiency. However, for end users, legacy applications need to be ported to ARM in order to properly work. To avoid this work, one can use an emulator to execute x86 binaries on an ARM system.
Goals of the thesis: You will study the design of various x86-to-ARM emulators (QEMU, FEX, box64) and evaluate their performance. In addition to this, you will also study the quality of the translated code and optimisation techniques, and compare them.
Target: B.Sc./M.Sc. students
Prerequisites:
- Previous knowledge emulation/computer architecture is appreciated
- Previous experience in reverse engineering is appreciated
Advisor: Redha Gouicem
Memory tiering systems have emerged as a promising solution for designing efficient memory subsystems, enabling machines with limited local memory to access a pool of remote memories. However, the higher latency associated with remote memory access makes data migration between local and remote memory a critical concern. To address this challenge, researchers are actively exploring efficient management schemes for memory tiering systems.
Goal & Steps: In this bachelor thesis, you will investigate existing management schemes through a comprehensive benchmarking study. Your goals and steps will include:
- Conducting an in-depth review of recent research papers on memory tiering systems, focusing on the benchmarks and evaluation methodologies
- Analyzing the performance of different management schemes using established benchmarks and emerging applications such as Artificial Intelligence, Bioinformatics, and Fog Computing, and developing microbenchmarks to explore corner cases
- Investigating the impact of Linux kernel tunables related to memory tiering (e.g., page migration thresholds, remote memory allocation policies, cache coherence settings) on the performance of memory tiering systems
Target: B.Sc. students
Prerequisites:
- Proficiency in C/C++ & Python programming
- Strong interest in system research
- Problem solving & research capability
Advisor: Mostafa Hadizadeh
Page table management is one of the main contributor to the overall performance of NUMA systems. Page table self-replication is one of the recent techniques that aims at addressing the challenges toward efficient management of NUMA systems.
Goal & Steps: In this thesis, you will investigate the impact of recent advances in TLB & page table management on NUMA systems’ efficiency:
- Reviewing recent kernel improvements with a focus on page table & TLB management
- Implementing the state-of-the-art schemes on top of the latest Linux kernel release
- Benchmarking each scheme & investigating statistics such as TLB flushes and shootdowns
Target: B.Sc./M.Sc. students
Prerequisites:
- Proficiency in C programming
- Strong interest in kernel development
- Basic knowledge of OS & computer architecture (address translation, TLB, page table)
- Problem solving & research capability
Advisor: Mostafa Hadizadeh
Computational Storage Devices (CSDs) are emerging devices aiming to improve the performance of computer systems by reducing data movement between storage & computation subsystems. Contrary to Von-Neumann paradigm where the data was delivered to central processing unit for computation, recent computational paradigms such as in-memory processing and computational storage devices introduce an alternative approach. By offloading a part of computation to CSD, the system can get rid of extra data movements, and accordingly, achieve higher performance.
Goal & Steps: In this thesis, you will explore CSD and the opportunities provided by this new paradigm:
- Setting-up an emulation/simulation CSD frameworks: 1) Exploring existing frameworks, 2) Evaluating existing the frameworks in terms of compliance with the standards such SNIA and NVMe
- Literature review with concentration on application domains that suites CSD paradigm
- Evaluating the impact of advanced compression algorithms on overall application performance and device lifetime
Target: M.Sc.
Prerequisites:
- Proficiency in C/C++ programming
- Problem solving & research capability
Advisor: Mostafa Hadizadeh